View TC78B002FNG_8136120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TC78B002FNG 2013- 10- 17 1 toshiba cmos integrated circuit silicon monolithic tc 7 8b002 f ng single phase full - wave driver for fan motor tc 78b00 2 fn g is a single phase full - wave d river for fan motor. it has a d mos device in an output transistor. a highly effective drive is possible by adopting a dmos output driver with low on resistance and a pwm drive system. features ? single -p hase f ull-w ave drive ? motor power supply voltage: vm =16v ( maximum operating range) ? output current: iout = 1. 5 a ( max. ) ? pwm control ? built - in oscillation circuit (external resistor) ? soft switching drive ? lock protection, automatic recovery ? quick start ? built in hall bias ? rotation speed detection (fg) and lock detection (rdo) output ? current limit function ? built in o ver current pro tection ? built in t hermal shut down circuit tc78b00 2 f n g weight : 0. 07 g ( typ ) ssop16 - p - 225 - 0.65b
TC78B002FNG 2013- 10- 17 2 block diagram (application circuit) 5 v regulator control logic pre driver tsd m lock protection osc hall ele . out 1 out 2 fg rdo rs vm gnd oscr vmi la hm hp vreg 7 bit a / d voff isd vsoft vsp 0 . 1 uf 24 k 0.1f
TC78B002FNG 2013- 10- 17 3 pin assignment vmi la voff vsoft 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vm gnd rs vsp fg out 1 out 2 oscr vreg hp hm rdo
TC78B002FNG 2013- 10- 17 4 pin description pin no. pin name description 1 vreg output pin for reference voltage of 5 v 2 hp hall signal input pin + 3 hm hall signal input pin 4 oscr connection pin for resistor of oscillation circuit 5 rdo output pin for lock detection 6 out1 motor output pin 1 7 gnd connection pin for ground 8 rs connection pin for detecting resistor of output current 9 vm power supply pin 10 out2 moto r output pin 2 11 fg rotating output pin 12 vsp setting pin for output duty 13 voff setting pin for off term in switching conducting phase 14 la setting pin for lead angle 15 vmi setting pin for minimum output duty 16 vsoft setting pin for soft switc hing t erm
TC78B002FNG 2013- 10- 17 5 absolute maximum ratings (ta = 25 c) characteristics symbol rating unit power supply voltage v m 18 v input voltage v in - 0.3~ 6 ( note 1) v output voltage v out 18 (note 2) v output current out1,out2 i out 1.5 (note 3 ) a vreg i out 10 m a fg pin s ink current i fg 10 ma rdo pin s ink current i rdo 10 ma power dissipation p d 0.96 ( note 4) w operating temperature t opr - 40 to 105 c storage temperature t stg - 55 to 150 c note : the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating (s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. please use the ic within the specified operating ranges. note 1: vmi , vsp , vsoft , voff , and la pins note 2 : out1 , out2 , fg and rdo pins note 3 : power dissipation must not be exceed note 4: mounted on a glass epoxy board package power dissipation (1) when mounted on the board ( 40mm 30mm 1.6mm 2 layers, fr - 4 board ) rth(j - a)=130 /w (2) ic only rth(j - a)=400 /w operating ranges (ta = 25 c) characteristics symbol min typ. max unit power supply voltage v m opr 1 5.5 12 16 v power supply for l ow voltage operation vm opr2 3.5 4.5 5.5 v internal oscillation frequency ( note 1) f osc 8 10 12 mhz pwm frequency f pwm 20 25 30 khz input voltage ( note 2) v in 0 ? v reg v note 1 : in low - voltage operation , operation with frequency more than 1 0mhz is not covered under guarantee. note 2: vmi , vsoft , voff , and la pins 0 0.2 0.4 0.6 0.8 1 1.2 0 25 50 75 100 125 150 p d (w) ta ( ) (1) (2)
TC78B002FNG 2013- 10- 17 6 electrical characteristics (ta = 25 c and v m = 12 v , unless otherwise specified. ) characteristics symbol test conditions min typ. max unit power supply current i vm v m = 1 2 v, v reg = open hall input=100hz , output open ? 3 5 ma hall signal input common mode input voltage range v cmrh 0 ? v reg - 1.5 v input voltage swing v h 40 ? ? mv input current i h |v hp - v hm | R 100mv ? ? 1 a hysteresis >) voltage v hhys+ ( design target value ) ( note 1) 5 10 15 mv hysteresis >+ voltage v hhys - ( design target value ) ( note 1) - 15 - 10 - 5 mv vreg pin voltage v reg vreg pin output source current =10ma 4.5 5.0 5.5 v maximum voltage of adc convertor v adc ( design target value ) ( note 1) ? v reg - 0.75 ? v output on duty ( note 1) duty( 20) r osc =24k , output load: n v sp = 1.2v , v mi =0v or v mi = 1.2v , v sp =0v 15 20 25 % duty(50) r osc =24k , output load: n v sp = 2.2v , v mi =0v or v mi = 2.2v , v sp =0v 43 50 57 % duty( 80) r osc = 24k , output load: n v sp = 3.2v , v mi =0v or v mi = 3.2v , v sp =0v 70 80 90 % vsp threshold v ad (l) threshold voltage of stopping output 0.5 0.55 ? v v ad (h) threshold voltage of full output ? 3.9 4.3 vsp response time t vsp (design target value) ( note 1) ? ? 10 ms internal oscillation frequency f osc r osc n measured by internal divided frequency 8 10 12 mhz pwm frequency f pwm r osc n 20 25 30 khz pin input current i in vsp,vmi,vsoft,voff, and la pins input voltage 0~v reg ? ? 1 a output on resistance ron(h+l) i out = 0.2a ? 1.6 2.5 soft switchin g time ( note 1) t soft (0) r osc n+doolsw + voff=0v , vsoft=0v ? ? 0 t soft (45) r osc n+doolsw + voff=0v , vsoft=v reg *0.45 43 ? 47 t soft (90) r osc n+doolsw + voff=0v , vsoft= v reg 84 ? 90 off term ( note 1) t off (0) r osc n+doolsw + vsoft=0v, voff=0v ? ? 0 t off (45) r osc n+doolsw + vsoft=0v, voff= v reg *0.45 43 ? 47 t off (90) r osc n+doolsw + vsoft=0v, voff= v reg 84 ? 90 lead angle correction ( note 1) t la (0) r osc n+dool nput=100hz la=0v ? ? 0 t la (11.25) r osc n+doolsw + la= v reg *0.23 10 ? 12 t la (22.5) r osc n+doolsw + la= v reg 21 ? 24
TC78B002FNG 2013- 10- 17 7 characteristics symbol test conditions min typ. max unit fg rdo pin output l ow voltage v out (l) i fg/rdo = 5 ma ? ? 0.3 v output leakage current i out (h) v fg/rdo =5v ? ? 1 a current limit detecting voltage for rs pin v rs 0.27 0.3 0.33 v masking time of current limit detection t mask (design target value) ( note 1) 1.2 1.5 1.8 s operating current of over current protection i lim (design target value) ( note 1) ? 2.5 ? a masking time of over current protection t isdmask (design target value) ( note 1) ? 2 ? s off time of over current protection t isdoff (design target value) ( note 1) ? 100 ? ms operating temperature of thermal shutdown circuit t sd junction temperature (d esign target value) ( note 1) ? 170 ? hysteresis of thermal shutdown circuit t sd (design target value) ( note 1) ? 40 ? on time of lock detection t on r osc =24k (design target value) ( note 1) 0.32 0.4 0.48 s off time of lock detection t off r osc =24k ( design target value) ( note 1) 3.2 4 4.8 s detecting voltage for low voltage v uvlo operation voltage (design target value) ( note 1) 2.6 2.9 3.2 v v porrl recovery voltage (design target value) ( note 1) 2.9 3.2 3.5 v output switching characteristics t r (d esign target value) ( note 1) ? 100 ? ns t f (design target value) ( note 1) ? 100 ? note 1: pre - shipment testing is not performed.
TC78B002FNG 2013- 10- 17 8 reference data fig.1 power supply current fig.2 hall input hysteresis voltage fig. 3 vreg pin voltage (vm=12v) fig.4 vreg pin voltage (ta=25 ) fig.5 output on resistance (vm=12v) fig.6 output on resistance ( ta = 2 5 ) - 20 - 10 0 10 20 3 6 9 12 15 18 hall input hysteresis voltage. v hhys [mv] supply voltage. vm[v] 125 25 - 40 operation voltage range - 40 25 125 4.6 4.7 4.8 4.9 5 0 2 4 6 8 10 vreg output voltage. v reg [v ] output current. i vreg [ma] 125 25 - 40 2 3 4 5 6 0 2 4 6 8 10 vreg output voltage. v reg [v ] output current. i vreg [ma] 18v 12v 3.5v 0 1 2 3 4 0 0.3 0.6 0.9 1.2 1.5 ouput on resistance.r on(h+l) [ ] output current. i out [a] 125 25 - 40 0 1 2 3 4 0 0.3 0.6 0.9 1.2 1.5 ouput on resistance.r on(h+l) [ ] output current. i out [a] 3.5v 12v 1 2 3 3 6 9 12 15 18 power supply current. i vm [ma] supply voltage. vm[v] 125 25 - 40 operation voltage range
TC78B002FNG 2013- 10- 17 9 fig.7 fg/rdo pin output l ow voltage (vm=12v) fig.8 fg/rdo pin output l ow voltage (ta=25 ) fig.9 internal oscillation frequency fig.10 current limit detecting voltage for rs pin 0 0.2 0.4 0.6 0.8 1 0 2 4 6 8 10 fg low voltage. v out(l) [v ] output current. i fg/ rdo [ma] 125 25 - 40 0 0.2 0.4 0.6 0.8 1 0 2 4 6 8 10 fg low voltage. v out(l) [v ] output current. i fg/rdo [ma] 3.5v 12v 8 9 10 11 12 3 6 9 12 15 18 internal oscillation frequency . f osc [mhz] supply voltage. vm[v] 125 25 - 40 operation voltage range 0.28 0.29 0.3 0.31 0.32 3 6 9 12 15 18 current limit detecting voltage . v r s [v] supply voltage. vm[v] 125 25 - 40 operation voltage range
TC78B002FNG 2013- 10- 17 10 i/o equivalent circuits pin name i/o signal equivalent circuit hp hm hall signal input pin in - phase input voltage range 0v to v reg - 1.5v vsp vmi la control voltage input pin vsoft voff co ntrol voltage input pin vreg voltage output pin v reg = 5v ( typ) fg rdo digital output pin open drain output it should be pulled up externally to output high. vsp vmi la fg rdo hp hm vreg vreg vsoft voff vreg vreg vm
TC78B002FNG 2013- 10- 17 11 pin name i/o signal equivalent circuit vm out1 out2 rs motor output pin oscr connection pin for resistor of oscillation ci rcuit out 1 out 2 vm rs 0 . 3 v oscr vreg vreg
TC78B002FNG 2013- 10- 17 12 functional description the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. timing charts may be simplified for explanatory purposes. 1. basic operation at startup, the motor is driven by a square - wave drive by determining the conducting phase with hall input signal. when hall signal frequency reaches 5 hz ( typ) or more, the motor is driven by the conducting pattern which is generated by estimating the next conducting timing from the hall i nput signal . < i/o function table > hp hm out1 out2 fg rdo mode h l l pwm off l r otating ( note 1) l h pwm l l l h l l off off ? current limit drive ( note 2) l h off l l ? ? ? off off ? off lock protection ( note 3) ? ? off off ? ? thermal shutdown n ote 1 conducting phase is switched by the hall input signal. fg signal is outputted according to the phase - switching. conducting timing may be preceded depending on the lead angle set. note 2 upper power transistor is turned off during current limitation. it r ecovers automatically every pwm frequency. note 3 fg output changes depending on the rotor position in the lock protection mode the same as rotating mode. timing chart ( normal rotation ) with soft switching, with lead angle without soft switching, without lead angle hp hm out1 out2 fg out1 out2 fg 0 < hall < 5hz 5hz < hall
TC78B002FNG 2013- 10- 17 13 timing chart ( lock protection ) 2. vsp / vmi input pin o utput sta rts when vsp pin at the voltage of more than v ad(l) . and it turns off at the voltage of v ad(l) or less. minimum voltage of vsp pin is clipped by the voltage of vmi pin. in case the minimum duty setting by vmi pin is not used , connect the vmi pin to the gnd pin. analog voltage which is input to vsp pin and vmi pin is converted by ad convertor of 7 bit, and the output pwm duty is controlled. 0 vsp, vmi v ad (l) duty = 0% v ad (l) < vsp, vmi v ad (h) below figure ( 1 7 /127 to 11 6 /127 ) v ad (h) < vsp, vmi v reg duty = 100% (11 7 /127 to 127/127 ) ( pwm duty indicates the peak value of output because this circuit has a soft switchin g function.) 3. hall input signal characteristics of hall signal shown below are inputted to the hall input pin. duty vsp 100% 0 v ad(l) v ad(h) vsp 100 % 0 vmi duty v ad ( l ) v ad ( h ) hp hm ?` ?R v reg v reg - 1 . 5 v gnd hp hm v h v hhys - v hhys + v h : 40mv or more v hhys+ =10mv, v hhys - = - 10mv *though hall amplifier operates when v h is 40mv or more, please widen the oscillation as possible to stabilize the time width. (200mv or more is recommended.) v oltage range of h all input hp - hm fg out2 out1 off (hi-z) off (hi- z) rdo t on t off
TC78B002FNG 2013- 10- 17 14 4. osc frequency and pwm frequency oscillation frequency is approximated by below formula. f osc = 1/( 2c [f]r osc []) [hz]= 1/(2 2.08e - 12[f]r osc []) [hz] oscillation frequency f osc is 10mhz (typ) when external resistor rosc is 24k pwm frequency f pwm =f osc /400. 5. pwm output drive in pwm drive, upper power transistor is turned on and off repeatedly. in switching phase, p ower transistor operates in below order. 6. startup sequence o utput starts when vsp pin at the voltage of v ad(l) or more. in order to ensure the starting torque , pwm output is 50% duty when the motor rotating speed is lower than 5hz (typ). when output phase is switched during startup sequence , pwm off term of 1ms ( typ) is inserted to reduce the regenerating current to the power supply. vm r f m rs vm r f m rs vm r f m rs pwm on pwm on off pwm on vm r f m rs vm r f m rs vm r f m rs vm r f m rs vm r f m rs pwm on pwm off pwm off pwm on short brake 200ns (design target value) 0.55v vsp hp hm off ?R? 50% duty output d uty is output by vsp voltage
TC78B002FNG 2013- 10- 17 15 7. turning off output turns off when the voltage of vsp pin is v ad(l) or less. before all output power transistors are t urned off , the time , until the edge of fg signal is detected twice or the frequency of 5 h z or less is detected, is defined pwm off term. vsp fg out 1 out 2 0 . 5 v off hi - z ) off hi - z ) off hi - z ) vsp fg out1 out2 0.5v off hi - z ) off hi - z ) off hi - z ) detecting 5hz or less 0.55v 0.55v
TC78B002FNG 2013- 10- 17 16 8. soft switching soft switching is performed by changing the output pwm duty gradually when conducting phas e switch es . the time of soft switching is determined by the voltage of vsoft pin and that of voff pin. t soft > t off t soft < t off voltage of vsoft > voltage of voff : total term of soft switching ( t soft ) is determined by the time of prior hall signal ( 180 ) and the voltage of vsoft pin. off term is provided during soft switching. the time of off term ( t off ) is determined by the prior hall signal ( 180 ) and the voltage of voff pin. during off term, the state of the power transistor is in the pwm off mo de. s oft switching operates in the period other than the off term , and o utput pwm duty changes by 16 s tep s in maximum. voltage of vsoft < voltage of voff : it does not have the term of soft switching operation which changes the duty, but it has the off term. off term ( t off ) is determined by the time of the prior hall signal ( 180 ) and the voltage of voff pin. during off term, the sate of the power transistor is in the pwm off mode. when next edge does not occur though time of t1 passes, last output sta te continues. conducting pattern is reset in synchronization with the up edge and the down edge of the hall signal. so, waveform indicates non - contiguous every reset when hall signal is offset and in speed up/slow down mode. hp-pm out1 out2 t1 t1' t off t soft t off t soft t soft ? ? ? t off t soft t off hp - pm out 1 out 2 t 1 t 1 ' t off t soft t off t soft
TC78B002FNG 2013- 10- 17 17 < relation between the voltage of vsoft pin and the term of soft switching > vsoft 0v 0 vsoft v adc 87.2 ( in case voltage of v adc or more is input, it is set to 87.2 . ) step vsoft (v) te r m () step vsoft (v) te r m () step vsoft (v) te r m () 1 0.00 0.0 12 1.51 30.9 23 3.02 61.9 2 0.14 2.8 13 1.65 33.8 24 3.15 64.7 3 0.27 5.6 14 1.78 36.6 25 3.29 67.5 4 0.41 8.4 15 1.92 39.4 26 3.43 70.3 5 0.55 11.3 16 2.06 42.2 27 3.56 73.1 6 0.69 14.1 17 2.19 45.0 28 3.70 75.9 7 0.82 16.9 18 2.33 47.8 29 3.84 78.8 8 0.96 19.7 19 2.47 50.6 30 3.98 81.6 9 1.10 22.5 20 2.60 53.4 31 4.11 84.4 10 1.23 25.3 21 2.74 56.3 32 4.25 87.2 11 1.37 28.1 22 2.88 59.1 term
TC78B002FNG 2013- 10- 17 18 < relation between the voltage of v off pin and the term of turn ing off > voff 0v 0 voff v adc 87.2 ( in case voltage of v adc or more is input, it is set to 87.2) step voff (v) te r m () step voff (v) te r m () step voff (v) te r m () 1 0.00 0.0 12 1.51 30.9 23 3.02 61.9 2 0.14 2.8 13 1.65 33.8 24 3.15 64.7 3 0.27 5.6 14 1.78 36.6 25 3.29 67.5 4 0.41 8.4 15 1.92 39.4 26 3.43 70.3 5 0.55 11.3 16 2.06 42.2 27 3.56 73.1 6 0.69 14.1 17 2.19 45.0 28 3.70 75.9 7 0.82 16.9 18 2.33 47.8 29 3.84 78.8 8 0.96 19.7 19 2.47 50.6 30 3.98 81.6 9 1.10 22.5 20 2.60 53.4 31 4.11 84.4 10 1.23 25.3 21 2.74 56.3 32 4.25 87.2 11 1.37 28.1 22 2.88 59.1 term
TC78B002FNG 2013- 10- 17 19 < pwm change during soft switching > soft switching after conducting phase switch: it changes gradually fro m 4% to 100% of output pwm duty determined by the voltage of vsp pin. its number of steps is 16 in maximum. soft switching before conducting phase switch: it changes gradually from 100% to 4% of output pwm duty determined by the voltage of vsp pin. its num ber of steps is 16 in maximum. in case the term of soft switching operation is 22.5 or less, number of steps is less than16 in the soft switching term . the relation of steps of soft switching and the output pwm duty ratio is shown below. step output ratio (%) step output ratio (%) step output ratio (%) 1 4 7 59 13 94 2 14 8 67 14 97 3 25 9 74 15 99 4 34 10 80 16 100 5 42 11 86 6 52 12 91 output ratio steps of pwm chan ge term of soft switching operation
TC78B002FNG 2013- 10- 17 20 9. lead angle lead angle of the conducting signal can be set in the range of 0 to 22.5 against the hall signal . lead angle is set by a nalog input of la pin ( the range of 0 to v adc is divided into 32 steps and low er 17 steps are used.) la 0v lead angle 0 la v adc lead angle 22.5 ( in case of inputting the voltage of v adc or more . ) step la (v) lead angle () step la (v) lead angle () step la (v) lead angle () 0 0.00 0.0 6 0.82 8.4 12 1.65 16.9 1 0.14 1.4 7 0.96 9.8 13 1.78 18.3 2 0.27 2.8 8 1.10 11.3 14 1.92 19.7 3 0.41 4.2 9 1.23 12.7 15 2.06 21.1 4 0.55 5.6 10 1.37 14.1 16 2.19 22.5 5 0.69 7.0 11 1.51 15.5 lead angle
TC78B002FNG 2013- 10- 17 21 10. lock protection it monitors the motor rotation by the hall signal and oper ates when the zero cross of the hall signal can not be detected for certain time (t on ) or more. w hen lock protection operates , t he upper output transistor is turned off for 1ms (typ) and then a ll output power transistors are turned off . the motor drive resu mes certain time (t off ) after the lock protection operates. t on = 0.4 s ( typ) t off = 4 s ( typ) fg is outputted by the hall signal even while the lock protection is operating. in case the zero cross of the hall signal is detected twice in re - startup, t he lock protection is cleare d and the rdo signal outputs low again. 11. quick start during t off of lock protection, lock protection is cleare d when the voltage of vsp pin is set to v ad(l) or less. when v ad(l) or more is applied to the v sp pin again, the moto r restart s operating quickly without waiting for the end of the t off t erm . because the voltage of vsp pin is detected through a/d circuit, the voltage of vsp pin should be kept at v ad(l) or less for vsp response time (t vsp ) or more in order to clear the lock protection. quick start is disabled when the minimum of the duty is configured by applying the voltage of v ad(l) or more to vmi pin. hp-hm fg out2 out1 off (hi-z) rdo t on t off t on off (hi-z) off (hi-z) off (hi-z) l l 20us 20us hp - hm fg out 2 out 1 rdo t on t off vsp 0 . 5 v off ( hi - z ) off ( hi - z ) l 20 us 1ms 1ms 1ms 0.55v
TC78B002FNG 2013- 10- 17 22 12. current limit this function operates when the output voltage reaches the current limit detection voltage (v rs = 0.3 v (typ) ). it is detected by the resistor r f . when r f =0. 51 , i out = 0.3v ( typ) /0.51 =588m a during the current limit oper ation, the operation mode is moved to pwm off state by turning off the upper output power transistor. the operation resumes at the next pwm on timing. masking time is configured to avoid malfunction by noise. ( in case hp = l and hm = h) current value which over current protection operate s (i out ) = over current detection voltage (v rs ) detection resistance (r f ) rs ?R ?? ?g 2us out1 out2 ? pwm 0.3v (typ) off hi - z ) off hi - z ) off hi - z ) off hi - z ) 1.5 s voltage of rs pin detection term of current limit internal pwm m out1 out2 vm rs r f i out 0.3v
TC78B002FNG 2013- 10- 17 23 13. over curren t protection (isd) detection of current of the output power transistor is incorporated. each current flowing through four power transistors is detected individually. when the current exceeds the detection value, the related output power transistor is turne d off. then all output power transistors are turned off 1ms(typ) after this related output power transistor is turned off. timer is incorporated in this circuit. the motor operation resumes off time of 100ms (typ) after the over current is detected. when s tate of over current continues, over current protection operates repeatedly. in case this protection operates 8 times repeatedly , the motor operation does not resume automatically. the output power transistor keeps turned off. in order to clear this state, vsp or the power supply should be applied again. design target value of current limit for over current protection is 2.5 a . masking term of 2 s (typ) is configured to avoid malfunction by noisy pulse current. 14. thermal shutdown circuit ( tsd) thermal shutd own circuit (tsd) operates when t j rises to 1 7 0 (typ) or more. all output power transistors are turned off after a 1ms(typ) pwm off term during which upper output power transistor is turned off . the operation resumes when the temperature falls to 13 0 (typ) or less. 15. under voltage lockout protection (uvlo ) this ic has an under voltage lockout protection ( uvlo). the power supply voltage of vm and the voltage of vreg are monitored. when each of them falls to 2.9 v ( typ ) or less, it is recognized as low volt age and the circuit is turned off. the normal operation resumes when both voltage recovers to 3.2v ( typ ) or more. 170 ( typ ) 130 ( typ ) gfggggegug ( t j ) 4 tsd 38 off fh hi - z ) pwm off 38 out 1 / out 2 1 ms junction temperature internal tsd signal normal operation normal operation 2 . 8 v ( typ ) 3 . 1 v ( typ ) vm 7 vreg 7 4 uvlo 07v 38 off fh hi - z ) 38 out 1 , out 2 fg , rdo uvlo 8 2.9v 3.2v vm voltage vreg v oltage internal uvlo release signal normal operation normal operation uvlo protection
TC78B002FNG 2013- 10- 17 24 package dimensions ssop16 -p- 225 - 0.65b unit: mm
TC78B002FNG 2013- 10- 17 25 notes on contents 1. block diagrams some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document are provided for reference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does n ot grant any license to any industrial property rights by providing these examples of application circuits. 5. test circuits components in the test circuits are used only to obtain and confirm the device characteristics. these components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. ic usage considerations notes on handling of ics [1] the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] use an appropriate power supply fuse to ensure that a large current d oes not continuously flow in case of over current and/or ic failure. the ic will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiri ng or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circu it location, are required. [3] if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power on or the negative current resulting from the back electromotive force at power off. ic breakdown may cause injury, smoke or ignition. use a stable power supply with ics with built - in protection functions. if the power supply is unstable, the protection fun ction may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. [4] do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. in addition, do not use any device t hat is applied the current with inserting in the wrong orientation or incorrectly even just one time.
TC78B002FNG 2013- 10- 17 26 points to remember on handling of ics (1) over current protection circuit over current protection circuits (referred to as current limiter circuits) do not necessarily protect ics under all circumstances. if the over current protection circuits operate against the over current, clear the over current status immediately. depending on the method of use and usage conditions, such as exceeding absolute ma ximum ratings can cause the over current protection circuit to not operate properly or ic breakdown before operation. in addition, depending on the method of use and usage conditions, if over current continues to flow for a long time after operation, the i c may generate heat resulting in breakdown. (2) thermal shutdown circuit thermal shutdown circuits do not necessarily protect ics under all circumstances. if the thermal shutdown circuits operate against the over temperature, clear the heat generation st atus immediately. depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or ic breakdown before operation. (3) heat radiation design in using an ic wit h large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (t j ) at any time and condition. these ics generate heat even during normal use. a n inadequate ic heat radiation design can lead to decrease in ic life, deterioration of ic characteristics or ic breakdown. in addition, please design the device taking into considerate the effect of ic heat radiation with peripheral components. (4) back - emf when a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motors power supply due to the effect of back - emf. if the current sink capability of the power supply is small, the devices motor power supply and output pins might be exposed to conditions beyond absolute maximum ratings. to avoid this problem, take the effect of back - emf into consideration in system design.
TC78B002FNG 2013- 10- 17 27 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (co llectively "toshiba"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "product") without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunct ion or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and system s which minimize risk and avoid situations in which a malfunction or failure of product coul d cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incor porate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the pr ecautions and conditions set forth in the "toshiba se miconductor reliability handbook" and (b) the instructions for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, inclu ding but not limited to (a) d etermining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circu its, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? product is neither intended nor warranted for use in equipm ents or systems that require extraordinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage and/or serious public impact ( " unintended use " ). except fo r specific applications as expressly stated in this document, unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automob iles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, eleva tors and escalators, devices related to electric power, and equipment used in finance - related fields. if you use product for uninte nded use, toshiba assumes no liability for product. for details, please contact your toshiba sales representative. ? do not disassemble, analyze, reverse - engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not b e used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no responsibility is assumed b y toshiba for any infringement of patents or any other intellectual property rights of third parties that may result from the use of product. n o license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provided in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect , consequential, special, or incidental damages or loss, including without limitation, loss of profits, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sal e, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). product and related software and tech nology may be controlled under the applicable export laws and regulations including, without limitation, the japanese foreign exchange and foreign trade law and the u.s. export administration regulat ions. export and re - export of product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pr oduct. please use pr oduct in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losse s occurring as a result of nonco mpliance with applic able laws and regula tions.

▲Up To Search▲

Price & Availability of TC78B002FNG

	To Download TC78B002FNG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .